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single supply, rail-to-rail, low cost instrumentation amplifier preliminary technical data AD8223 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?200 8 analog devices, inc. all rights reserved. features gain set with 1 resistor per amplifier gain = 5 to 1000 inputs voltage range to 150 mv below negative rail 25 na maximum input bias current 30 nv/hz, rti noise @ 1 khz power supplies dual supply: 2.5v to 12.5 single supply: 3v to 25v 600 a maximum supply current connection diagram ?r g 1 ?in 2 +in 3 ?v s 4 +r g 8 +v s 7 output 6 ref 5 ? + AD8223 06925-001 figure 1. 8-lead soic (r) and 8-lead msop soic (rm) packages applications low power medical instrumentation transducer interface thermocouple amplifiers industrial process controls difference amplifiers low power data acquisition general description the AD8223 is an integrated single-supply instrumentation amplifier that delivers rail-to-rail output swing on a single supply (+3.0 v to +25 v supplies). the AD8223 offers superior user flexibility by allowing single-gain set resistor program- ming, and conforming to the 8-lead industry standard pinout configuration. with no external resistor, the AD8223 is configured for g = 5 and with an external resistor, the AD8223 can be programmed for gains up to 1000. the AD8223 holds errors to a minimum by providing superior ac cmrr that increases with increasing gain. line noise, as well as line harmonics, is rejected because the cmrr remains constant up to 200 hz. the AD8223 has a wide input common- mode range and can amplify signals that have a common-mode voltage 150 mv below ground. although the design of the AD8223 is optimized to operate from a single supply, the AD8223 still provides superior performance when operated from a dual voltage supply (2.5 v to 12.5 v). low power consumption (1.5 mw at 3 v), wide supply voltage range, and rail-to-rail output swing make the AD8223 ideal for battery-powered applications. the rail-to-rail output stage maximizes the dynamic range when operating from low supply voltages. the AD8223 replaces discrete instrumentation amplifier designs and offers superior linearity, temperature stability and reliability in a minimum of space.
AD8223 preliminary technical data rev. pra | page 2 of 20 table of contents features .............................................................................................. 1 connection diagram ....................................................................... 1 applications....................................................................................... 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications..................................................................................... 3 single supply ................................................................................. 3 dual supply ................................................................................... 5 absolute maximum ratings............................................................ 7 esd caution.................................................................................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 13 amplifier architecture .............................................................. 13 gain selection ............................................................................. 13 input voltage range................................................................... 13 reference terminal .................................................................... 14 input protection ......................................................................... 14 rf interference ........................................................................... 14 ground returns for input bias currents ................................ 15 applications information .............................................................. 16 basic connection ....................................................................... 16 differential output .................................................................... 16 output buffering ........................................................................ 16 cables........................................................................................... 16 a single-supply data acquisition system .............................. 17 amplifying signals with low common-mode voltage........ 17 outline dimensions ....................................................................... 18 ordering guide .......................................................................... 19 revision history
preliminary technical data AD8223 rev. pra | page 3 of 20 specifications single supply t a = 25c, single supply, v s = +5 v, and r l = 10 k, unless otherwise noted. table 1 AD8223a AD8223b parameter conditions min typ max min typ max unit common mode rejection ratio dc to 60 hz with 1 k source imbalance v cm = 0 v to 3 v g = 5 74 86 db g = 10 80 92 db g = 100 88 100 db g = 1000 88 100 db noise voltage noise, 1 khz g = 5 50 50 nv/hz g = 1000 30 30 nv/hz rti, 0.1 hz to 10 hz g = 5 3.0 3.0 v p-p g = 1000 1.5 1.5 v p-p current noise, 1 khz 100 100 fa/hz 0.1 hz to 10 hz 1.5 1.5 pa p-p voltage offset total rti error = v osi + v oso /g input offset, v osi 400 200 v average tc 5 3 v/c output offset, v oso 1000 500 v average tc 15 10 v/c offset referred to input vs. supply (psr) g = 5 80 90 db g = 10 86 96 db g = 100 90 100 db g = 1000 90 100 db input current input bias current 17 25 17 25 na over temperature 27.5 27.5 na average temperature coefficient 25 25 pa/c input offset current 0.25 2 0.25 2 na over temperature 2.5 2.5 na average temperature coefficient 5 5 pa/c dynamic response small signal ?3 db bandwidth g = 5 200 200 khz g = 10 190 190 khz g = 100 75 75 khz g = 1000 8 8 khz slew rate 0.3 0.3 v/s
AD8223 preliminary technical data rev. pra | page 4 of 20 AD8223a AD8223b parameter conditions min typ max min typ max unit settling time to 0.01% step size = 3.5 v g = 5 s g = 100 s g = 1000 s gain g = 5 + (80 k/r g ) gain range 5 1000 5 1000 v/v gain error 1 v out = 0.05 v to 4.5 v g = 5 0.03 0.15 0.03 0.1 % g = 10 0.10 1 0.10 0.5 % g = 100 0.10 1 0.10 0.5 % g = 1000 0.10 1 0.10 0.5 % nonlinearity v out = 0.05 v to 4.5 v g = 5 to 1000 50 50 ppm gain vs. temperature g = 5 5 10 5 10 ppm/c g > 5 1 50 50 ppm/c input input impedance differential 2||2 2||2 g||pf common-mode 2||2 2||2 g||pf input voltage range 2 (?v s ) ? 0.15 (+v s ) ? 1.5 (?v s ) ? 0.15 (+v s ) ? 1.5 v output output swing r l = 10 k to ground +0.01 (+v s ) ? 0.5 +0.01 (+v s ) ? 0.5 v r l = 100 k to ground +0.01 (+v s ) ? 0.2 +0.01 (+v s ) ? 0.2 v reference input r in 60 20% 60 20% k i in v in +, v ref = 0 +50 +60 +50 +60 a voltage range ?v s +v s ?v s +v s v gain to output 1 0.0002 1 0.0002 v power supply operating range +3.0 +25 +3.0 +25 v quiescent current 550 550 a temperature range for specified performance -40 +85 ?40 +85 c 1 does not include effects of external resistor rg. 2 one input grounded. g = 1.
preliminary technical data AD8223 rev. pra | page 5 of 20 dual supply t a = 25c, dual supply, v s = 12 v, and r l = 10 k, unless otherwise noted. table 2. AD8223a AD8223b parameter conditions min typ max min typ max unit common mode rejection ratio dc to 60 hz with 1 k source imbalance v cm = ?10 v to 10 v g = 5 74 86 db g = 10 80 92 db g = 100 88 100 db g = 1000 88 100 db noise voltage noise, 1 khz g = 5 50 50 nv/hz g = 1000 30 30 nv/hz rti, 0.1 hz to 10 hz g = 5 3.0 3.0 v p-p g = 1000 1.5 1.5 v p-p current noise, 1 khz 100 100 fa/hz 0.1 hz to 10 hz 1.5 1.5 pa p-p voltage offset total rti error = v osi + v oso /g input offset, v osi 400 200 v average tc 5 3 v/c output offset, v oso 1000 500 v average tc 15 10 v/c offset referred to input vs. supply (psr) g = 5 80 90 db g = 10 86 96 db g = 100 90 100 db g = 1000 90 100 db input current input bias current 17 25 17 25 na over temperature 27.5 27.5 na average temperature coefficient 25 25 pa/c input offset current 0.25 2 0.25 2 na over temperature 2.5 2.5 na average temperature coefficient 5 5 pa/c dynamic response small signal ?3 db bandwidth g = 5 200 200 khz g = 10 190 190 khz g = 100 75 75 khz g = 1000 8 8 khz slew rate 0.3 0.3 v/s settling time to 0.01% step size = 10 v g = 5 30 30 s g = 100 30 30 s g = 1000 140 140 s
AD8223 preliminary technical data rev. pra | page 6 of 20 AD8223a AD8223b parameter conditions min typ max min typ max unit gain g = 5 + (80 k/r g ) gain range 5 1000 5 1000 v/v gain error 1 v out = ?10 v to +10 v g = 5 0.03 0.15 0.03 0.1 % g = 10 0.10 1 0.10 0.5 % g = 100 0.10 1 0.10 0.5 % g = 1000 0.10 1 0.10 0.5 % nonlinearity v out = ?10 v to +10 v g = 5 to 1000 50 50 ppm gain vs. temperature g = 5 5 10 5 10 ppm/ c g > 5 1 50 50 ppm/ c input input impedance differential 2||2 2||2 g||pf common-mode 2||2 2||2 g||pf input voltage range 2 (?v s ) ? 0.15 (+v s ) ? 1.5 (?v s ) ? 0.15 (+v s ) ? 1.5 v output output swing r l = 10 k to ground (?v s ) + 0.2 (+v s ) ? 0.5 (?v s ) + 0.2 (+v s ) ? 0.5 v r l = 100 k to ground (?v s ) + 0.1 (+v s ) ? 0.2 (?v s ) + 0.1 (+v s ) ? 0.2 v reference input r in 60 20% 60 20% k i in v in +, v ref = 0 +50 +60 +50 +60 a voltage range ?v s +v s ?v s +v s v gain to output 1 0.0002 1 0.0002 v power supply operating range 2.5 12.5 2.5 12.5 v quiescent current 600 600 a temperature range for specified performance ?40 +85 ?40 +85 c 1 does not include effects of external resistor rg. 2 one input grounded. g = 1.
preliminary technical data AD8223 rev. pra | page 7 of 20 absolute maximum ratings table 3. parameter rating supply voltage 12.5 v internal power dissipation 650 mw differential input voltage 6 v output short-circuit duration indefinite storage temperature range (r, rm) ?65c to +125c operating temperature range (a) ?40c to +85c lead temperature (soldering 10 sec) +300c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. specification is for device in free air. table 4. thermal resistance package type ja unit 8-lead soic 155 c/w 8-lead msop 200 c/w esd caution
AD8223 preliminary technical data rev. pra | page 8 of 20 typical performance characteristics t a = 25c v s = 5 v, r l = 10 k, unless otherwise noted. 50 0 ?200 200 06925-003 input offset voltage (v) number of units 40 30 20 10 ?150 ?100 ?50 0 50 100 150 figure 2. typical distributi on of input offset voltage 0 0 06925-004 input bias current (na) number of units 80 70 60 50 40 30 20 10 3 6 9 12 15 18 21 24 figure 3. typical distributi on of input bias current 0 06925-005 cmrr, g = 5 (v/v) number of units 80 60 40 20 ?40 ?20 0 20 40 figure 4. typical distribution for cmrr (g = 5) 0 06925-006 cmrr, g = 100 (v/v) number of units 40 35 30 25 20 15 10 5 ?9 ?6 ?3 0 3 6 9 figure 5. typical distribution for cmrr (g = 100) 1000 10 0.1 100k 06925-050 frequency (hz) voltage noise (nv/ hz) 1 10 100 1k 10k 100 g = 1000 bw limit g = 100 bw limit g = 5 g = 10 figure 6. voltage noise spectral density vs. frequency 30 15 0 25 20 10 5 temperature (c) i bias (na) ?60 ?40 ?20 0 20 40 60 80 100 120 140 06925-011 figure 7. i bias vs. temperature
preliminary technical data AD8223 rev. pra | page 9 of 20 1k 100 10 11k 10 100 frequency (hz) current noise (fa/ hz) 06925-012 figure 8. current noise spectral density vs. frequency 18 0 ?12 10 06925-013 cmv (v) i bias (na) 16 14 12 10 8 6 4 2 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 v s = 12v v s = 5v v s = 2.5v figure 9. i bias vs. cmv 06925-014 1s/div 0.71pa/div figure 10. 0.1 hz to 10 hz current noise (0.71 pa/div) 06925-054 1s/div 0.5v/div g = 5 g = 1000 figure 11. 0.1 hz to 10 hz rti and rto voltage noise 120 30 1100k 06925-055 frequency (hz) cmrr (db) 10 100 1k 10k 110 100 90 80 70 60 50 40 g = 5 g = 1000 g = 10 g = 100 figure 12. cmrr vs. frequency, 12 v s 120 30 1100k 06925-056 frequency (hz) cmrr (db) 10 100 1k 10k 110 100 90 80 70 60 50 40 g = 5 g = 1000 g = 10 g = 100 figure 13. cmrr vs. frequency, v s = +5 v
AD8223 preliminary technical data rev. pra | page 10 of 20 70 ?30 100 1m frequency (hz) gain (db) 1k 10k 100k 60 50 40 30 20 10 0 ?10 ?20 g = 1000 g = 100 g = 10 g = 5 06925-018 figure 14. gain vs. frequency 6 ?6 ?6 6 06925-057 output (v) common-mode input (v) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?5?4?3?2?1012345 v s = 5v v s = 2.5v v s = +5v figure 15. common-mode input vs. maximum output voltage, g = 5, small supplies 16 ?14 ?14 16 06925-058 output (v) common-mode input (v) 14 12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?12?10?8?6?4?202468101214 v s = 12v +v s = +15v, ?v s = ?5v figure 16. common-mode input vs. maximum output voltage, g = 5, large supplies 6 ?6 ?6 6 06925-059 output (v) common-mode input (v) 5 4 3 2 1 0 ?1 ?2 ?3 ?4 ?5 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 v s = 2.5v v s = +5v v s = 5v figure 17. common-mode input vs. maximum output voltage, g = 100, small supplies 16 ?14 ?14 18 06925-060 output (v) common-mode input (v) 14 12 10 8 6 4 2 0 ?2 ?4 ?6 ?8 ?10 ?12 ?12 ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 12 14 16 v s = 12v +v s = +15v, ?v s = ?5v figure 18. common-mode input vs. maximum output voltage, g = 100, large supplies 140 0 1 100k frequency (hz) psrr (db) 10 100 1k 10k 120 100 80 60 40 20 g = 1000 g = 10 g = 5 g = 100 06925-023 figure 19. positive psrr vs. frequency, v s = 12 v
preliminary technical data AD8223 rev. pra | page 11 of 20 140 0 1 100k frequency (hz) psrr (db) 10 100 1k 10k 120 100 80 60 40 20 g = 1000 g = 5 g = 100 g = 10 06925-024 figure 20. positive psrr vs. frequency, v s = 5 v 120 0 1 100k frequency (hz) psrr (db) 10 100 1k 10k g = 1000 g = 10 06925-025 100 80 60 40 20 g = 100 g = 5 figure 21. negative psrr vs. frequency, v s = 12 v figure 22. settling time to 0.005% vs . gain, for a 20 v step at output, c l = 100 pf, v s = 12 v 06925-051 100s/div 0.1%/div 5v/div figure 23. large signal response, g = 5 06925-052 100s/div 0.1%/div 5v/div figure 24. large signal pulse response, g = 100, c l = 100 pf 06925-053 100s/div 0.1%/div 5v/div figure 25. large signal pulse response, g = 1000, c l = 100 pf
AD8223 preliminary technical data rev. pra | page 12 of 20 06925-028 2 g = 100 g = 5 g = 10 10s/div 20mv/div figure 26. small signal pulse response, g = 5, 10, 100; r l = 10 k 06925-034 2 100s/div 20mv/div figure 27. small signal pulse response, g = 1000, r l = 25 k, c l = 100 pf 0.01 0.1 1 10 06925-037 i out (ma) output voltage swing (v) referred to supply voltages ?v s 1 2 ?2 ?1 + v s figure 28. output voltage swing vs. output current
preliminary technical data AD8223 rev. pra | page 13 of 20 theory of operation amplifier architecture the AD8223 is an instrumentation amplifier based on a classic 3-op amp approach, modified to assure operation even at common-mode voltages at the negative supply rail. the architecture allows lower voltage offsets, better cmrr, and higher gain accuracy than competing instrumentation amplifiers in its class. + ? 8k ? 10k ? 50k ? positive supply 7 invertin g 2 1 4 8k ? 10k ? 50k ? 8 4 negative supply non- invertin g 3 7 gain out 6 ref 5 + ? + ? 06925-038 figure 29. simpli fied schematic figure 29 shows a simplified schematic of the AD8223. the AD8223 has three stages. in the first stage, the input signal is applied to pnp transistors. these pnp transistors act as voltage buffers and allow input voltages below ground. the second stage consists of a pair of 8 k resistors, the r g resistor, and a pair of amplifiers. this stage allows the amplification of the AD8223 to be set with a single external resistor. the third stage is a differential amplifier composed of an op amp, two 10 k resistors, and two 50 k resistors. this stage removes the common mode signal and applies an additional gain of 5. the transfer function of the AD8223 is v out = g ( v in+ ? v in? ) + v ref where: g r g k 0 8 5 + = gain selection placing a resistor across the r g terminals sets the gain of the AD8223, which can be calculated by referring to table 5 or by using the following gain equation: 5 k 80 ? = g r g table 5. gains achieved sing 1 resistors 1% standard table value of r g () desired gain calculated gain 26.7k 8 7.99 15.8k 10 10.1 5.36k 20 19.9 2.26k 40 40.4 1.78k 50 49.9 845 100 99.7 412 200 199 162 500 499 80.6 1000 998 the AD8223 defaults to g = 5 when no gain resistor is used. the tolerance and gain drift of the r g resistor should be added to the specifications of the AD8223 to determine the total gain accuracy of the system. when the gain resistor is not used, gain error and gain drift are kept to a minimum. input voltage range the 3-op amp architecture of the AD8223 applies gain and then removes the common-mode voltage. therefore, internal nodes in the AD8223 experience a combination of both the gained signal and the common-mode signal. this combined signal can be limited by the voltage supplies even when the individual input and output signals are not. to determine whether the signal can be limited, refer to figure 15 through figure 18. alternatively, use the parameters in the specifications section to verify that the input and output are not limited and then use the following formula to make sure the internal nodes are not limited: to check if it is limited by the internal nodes, v 1 . 0 10 6 . 0 v 01 . 0 ? + < + < + ? s diff cm s v gain v v v if more common-mode range is required, a solution is to apply less gain in the instrumentation amplifier and more in a later stage.
AD8223 preliminary technical data rev. pra | page 14 of 20 reference terminal the output voltage of the AD8223 is developed with respect to the potential on the reference terminal. this is useful when the output signal needs to be offset to a precise midsupply level. for example, a voltage source can be tied to the ref pin to level- shift the output so that the AD8223 can drive a single-supply adc. the ref pin is protected with esd diodes and should not exceed either +v s or ?v s by more than 0.3 v. for best performance, source impedance to the ref terminal should be kept below 5 . as shown in figure 29, the reference terminal, ref, is at one end of a 50 k resistor. additional impedance at the ref terminal adds to this resistor and results in poorer cmrr performance. incorrect AD8223 v ref correct AD8223 op2177 + ? v ref 06925-039 figure 30. driving the reference pin input protection internal supply referenced clamping diodes allow the input, reference, output, and gain terminals of the AD8223 to safely withstand overvoltages of 0.3 v above or below the supplies. this is true for all gains, and for power-on and power-off. this last case is particularly important because the signal source and amplifier may be powered separately. if the overvoltage is expected to exceed this value, the current through these diodes should be limited to about 10 ma using external current limiting resistors. this is shown in figure 31. the size of this resistor is defined by the supply voltage and the required overvoltage protection. 10ma 1 = 10ma max output AD8223 + ? v over ? v s + 0.7v + v s ?v s r g r lim r lim r lim = v over v over 06925-040 figure 31. input protection rf interference rf rectification is often a problem when amplifiers are used in applications where there are strong rf signals. the disturbance can appear as a small dc offset voltage. high frequency signals can be filtered with a low-pass, r-c network placed at the input of the instrumentation amplifier, as shown in figure 32. the filter limits the input signal bandwidth according to the follow- ing relationship: ) (2 2 1 c d diff c c r filterfreq + = c cm rc filterfreq = 2 1 where c d 10 c c . r r AD8223 +15 v +in ?in 0.1f 10f 10f 0.1f ref v out ?15v r1 499 ? c d 47nf c c 1nf c c 1nf 4.02k ? 4.02k ? + ? + + 06925-041 figure 32. rfi suppression figure 32 shows an example where the differential filter frequency is approximately 400 hz, and the common-mode filter frequency is approximately 40 khz. the typical dc offset shift over frequency is less than 1.5 v and the circuits rf signal rejection is better than 71 db. the resistors were selected to be large enough to isolate the circuits input from the capacitors, but not large enough to significantly increase the circuits noise. values of r and c c should be chosen to minimize rfi. mismatch between the r c c at the positive input and the r c c at negative input degrades the cmrr of the AD8223. because of their higher accuracy and stability, cog/npo type ceramic capacitors are recommended for the c c capacitors. the dielectric for the c d capacitor is not as critical.
preliminary technical data AD8223 rev. pra | page 15 of 20 ground returns for input bias currents input bias currents are those dc currents that must flow to bias the input transistors of an amplifier. these are usually transistor base currents. when amplifying floating input sources such as transformers or ac-coupled sources, there must be a direct dc path into each input so that the bias current can flow. figure 33 shows how a bias current path can be provided for the cases of transformer coupling, capacitive ac-coupling and for a thermocouple application. in dc-coupled resistive bridge applications, providing this path is generally not necessary as the bias current simply flows from the bridge supply through the bridge and into the amplifier. however, if the impedances that the two inputs see are large and differ by a large amount (>10 k), the offset current of the input stage causes dc errors proportional with the input offset voltage of the amplifier. thermocouple +v s ref ?v s AD8223 capacitively coupled +v s ref c c ?v s AD8223 transformer +v s ref ?v s AD8223 incorrec t capacitively coupled +v s ref c r r c ?v s AD8223 1 f high-pass = 2 rc thermocouple +v s ref ?v s 10m ? AD8223 transformer +v s ref ?v s AD8223 correct 0 6925-042 figure 33. creating an i bias path
AD8223 preliminary technical data rev. pra | page 16 of 20 applications information +2.5v to +6v ref (input) ?2.5v to ?6v ref output +3v to +12v + ? + ? + v s 10f 0.1f 10f 0.1f 10f 0.1f + + v out + r g r g r g v in ?v s ref (input) ref output + v s v out r g r g r g v in a. dual supply b. single supply 06925-043 figure 34. basic connections basic connection figure 34 shows the basic connection circuit for the AD8223. the +v s and ?v s terminals are connected to the power supply. the supply can be either bipolar (v s = 2.5 v to 12.5 v) or single supply (?v s = 0 v, +v s = +3.0 v to +25 v). power supplies should be capacitively decoupled close to the devices power pins. for best results, use surface-mount 0.1 f ceramic chip capacitors and 10 f electrolytic tantalum capacitors. the input voltage, which can be either single-ended (tie either ?in or +in to ground) or differential, is amplified by the programmed gain. the output signal appears as the voltage difference between the output pin and the externally applied voltage on the ref input. differential output figure 35 shows how to create a differential output in-amp. a op1177 op amp creates the inverted output. because the op amp drives the AD8223 reference pin, the AD8223 can still ensure that the differential voltage is correct. errors from the op amp or mismatched resistors are common to both outputs and are thus common mode. these common-mode errors should be rejected by the next device in the signal chain. +in ?in ref AD8223 v ref 20k ? + ? op1177 +out ?out 20k ? figure 35. differential output using op amp output buffering the AD8223 is designed to drive loads of 10 k or greater. if the load is less than this value, the AD8223 output should be buffered with a precision single-supply op amp such as the op113 . this op amp can swing from 0 v to 4 v on its output while driving a load as small as 600 . 5 v AD8223 ref op113 5v v out + ? 0.1f 0.1f + ? v in r g 06925-045 figure 36. output buffering cables receiving from a cable in many applications, shielded cables are used to minimize noise; for best cmr over frequency, the shield should be properly driven. figure 37 shows an active guard drive that is configured to improve ac common-mode rejection by bootstrapping the capacitances of input cable shields, thus minimizing the capacitance mismatch between the inputs. r g 2 ?input +input 100 ? AD8223 ad8031 reference v out r g 2 +v s ?v s 2 7 6 5 4 1 8 3 06925-046 figure 37. common-mode shield driver
preliminary technical data AD8223 rev. pra | page 17 of 20 driving a cable all cables have a certain capacitance per unit length, which varies widely with cable type. the capacitive load from the cable may cause peaking in the AD8223s output response. to reduce the peaking, use a resistor between the AD8223 and the cable. because cable capacitance and desired output response vary widely, this resistor is best determined empirically. a good starting point is 50 . the ad8232 operates at a low enough frequency that transmission line effects are rarely an issue; therefore, the resistor need not match the characteristic impedance of the cable. AD8223 (diff out) AD8223 (single out) 06925-047 figure 38. driving a cable a single-supply data acquisition system interfacing bipolar signals to single-supply analog-to-digital converters (adcs) presents a challenge. the bipolar signal must be mapped into the input range of the adc. figure 39 shows how this translation can be achieved. 10mv 5v AD8223 ref 5v ad7776 5 v + ? a in ref out ref in 0.1f 0.1f r g 1.02k ? 0 6925-048 figure 39. a single supply data acquisition system the bridge circuit is excited by a +5 v supply. the full-scale output voltage from the bridge (10 mv) therefore has a common-mode level of 2.5 v. the AD8223 removes the common-mode component and amplifies the input signal by a factor of 100 (r gain = 1.02 k). this results in an output signal of 1 v. to prevent this signal from running into the AD8223 ground rail, the voltage on the ref pin has to be raised to at least 1 v. in this example, the 2 v reference voltage from the ad7776 adc is used to bias the AD8223 output voltage to 2 v 1 v. this corresponds to the input range of the adc. amplifying signals with low common- mode voltage because the common-mode input range of the AD8223 extends 0.1 v below ground, it is possible to measure small differential signals that have low, or no, common-mode components. figure 40 shows a thermocouple application where one side of the j-type thermocouple is grounded. 2v 5 v AD8223 ref 0.1f v out r g 1.02k ? + ? j-type thermocouple 06925-049 figure 40. amplifying bipolar sign als with low common-mode voltage over a temperature range from ?200c to +200c, the j-type thermocouple delivers a voltage ranging from ?7.890 mv to 10.777 mv. a programmed gain on the AD8223 of 100 (r g = 845) and a voltage on the AD8223 ref pin of 2 v results in the AD8223 output voltage ranging from 1.110 v to 3.077 v relative to ground.
AD8223 preliminary technical data rev. pra | page 18 of 20 outline dimensions compliant to jedec standards mo-187-aa 0.80 0.60 0.40 8 0 4 8 1 5 pin 1 0.65 bsc seating plane 0.38 0.22 1.10 max 3.20 3.00 2.80 coplanarity 0.10 0.23 0.08 3.20 3.00 2.80 5.15 4.90 4.65 0.15 0.00 0.95 0.85 0.75 figure 41. 8-lead mini small outline package [msop] (rm-8) dimensions shown in millimeters controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-a a 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 42. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches)
preliminary technical data AD8223 rev. pra | page 19 of 20 ordering guide model temperature range package description package option branding AD8223ar ?40c to +85c 8-lead soic_n r-8 AD8223ar-rl ?40c to +85c 8-lead soic_n,13" tape and reel r-8 AD8223ar-r7 ?40c to +85c 8-lead soic_n, 7" tape and reel r-8 AD8223arm ?40c to +85c 8-lead msop rm-8 y0u AD8223arm-rl ?40c to +85c 8-lead msop, 13" tape and reel rm-8 y0u AD8223arm-r7 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 y0u AD8223armz 1 ?40c to +85c 8-lead msop rm-8 y0q AD8223armz-rl 1 ?40c to +85c 8-lead msop, 13" tape and reel rm-8 y0q AD8223armz-r7 1 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 y0q AD8223arz 1 ?40c to +85c 8-lead soic_n r-8 AD8223arz-rl 1 ?40c to +85c 8-lead soic_n, 13" tape and reel r-8 AD8223arz-r7 1 ?40c to +85c 8-lead soic_n, 7" tape and reel r-8 AD8223br ?40c to +85c 8-lead soic_n r-8 AD8223br-rl ?40c to +85c 8-lead soic_n, 13" tape and reel r-8 AD8223br-r7 ?40c to +85c 8-lead soic_n, 7" tape and reel r-8 AD8223brm ?40c to +85c 8-lead msop rm-8 y0v AD8223brm-rl ?40c to +85c 8-lead msop , 13" tape and reel rm-8 y0v AD8223brm-r7 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 y0v AD8223brmz 1 ?40c to +85c 8-lead msop rm-8 y0r AD8223brmz-rl 1 ?40c to +85c 8-lead msop, 13" tape and reel rm-8 y0r AD8223brmz-r7 1 ?40c to +85c 8-lead msop, 7" tape and reel rm-8 y0r AD8223brz 1 ?40c to +85c 8-lead soic_n r-8 AD8223brz-rl 1 ?40c to +85c 8-lead soic_n, 13" tape and reel r-8 AD8223brz-r7 1 ?40c to +85c 8-lead soic_n, 7" tape and reel r-8 1 z = rohs compliant part.
AD8223 preliminary technical data rev. pra | page 20 of 20 notes ?200 8 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. pr06925-0-1/08(pra)

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